Semiconductor manufacturing apparatus and semiconductor manufacturing method

ABSTRACT

In one embodiment, a semiconductor manufacturing apparatus includes a stage provided in a chamber, and a conveying module configured to convey a plurality of wafers into the chamber and to set the plurality of wafers on the stage. The apparatus further includes a controller configured to divide treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and to change positions of one or more of the plurality of wafers on the stage by the conveying module according to the treatment periods.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2014-177458, filed on Sep. 1,2014, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor manufacturingapparatus and a semiconductor manufacturing method.

BACKGROUND

Semiconductor manufacturing apparatuses are classified into asingle-wafer treatment apparatus for treating a wafer individually and abatch treatment apparatus for treating plural wafers simultaneously. Thebatch treatment apparatus is advantageous that the plural wafers can betreated in a short time. However, since treatment speeds of the wafersdiffer depending on positions of the wafers in the batch treatmentapparatus, characteristics of the wafers may vary among the wafers. Onthe other hand, the single-wafer treatment apparatus is advantageousthat the variation of the characteristics can be suppressed amongwafers. However, the single-wafer treatment apparatus takes a long timeto treat plural wafers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a perspective view and a top view illustrating astructure of a semiconductor manufacturing apparatus of a firstembodiment;

FIGS. 2A to 2C are drawings for explaining a semiconductor manufacturingmethod of the first embodiment;

FIG. 3 is a graph for explaining advantages of the semiconductormanufacturing method of the first embodiment;

FIGS. 4A and 4B are cross sectional view for explaining advantages ofthe semiconductor manufacturing method of the first embodiment;

FIG. 5 is a drawing for explaining a semiconductor manufacturing methodof a second embodiment;

FIG. 6 is a block diagram for explaining operation of a controller ofthe second embodiment; and

FIG. 7 is a flowchart for explaining the semiconductor manufacturingmethod of the second embodiment.

DETAILED DESCRIPTION

Embodiments will now be explained with reference to the accompanyingdrawings.

In one embodiment, a semiconductor manufacturing apparatus includes astage provided in a chamber, and a conveying module configured to conveya plurality of wafers into the chamber and to set the plurality ofwafers on the stage. The apparatus further includes a controllerconfigured to divide treatment time for simultaneously treating theplurality of wafers on the stage into first to K-th treatment periodswhere K is an integer of two or more, and to change positions of one ormore of the plurality of wafers on the stage by the conveying moduleaccording to the treatment periods.

First Embodiment

FIGS. 1A and 1B are a perspective view and a top view illustrating astructure of a semiconductor manufacturing apparatus of a firstembodiment.

As shown in FIGS. 1A and 1B, the semiconductor manufacturing apparatusof the present embodiment includes a chamber 1, a cassette loadingmodule 2, a stage 3, a conveying arm 4 as an example of a conveyingmodule, a gas feeder 5 and a controller 6. The chamber 1 includes a gassupplying port 1 a for supplying a gas into the chamber 1 and a gasdischarging port 1 b for discharging the gas from the chamber 1.

FIG. 1A is a perspective view illustrating an external appearance of thesemiconductor manufacturing apparatus of the present embodiment. FIG. 1Bis a top view illustrating the stage 3 and the like provided in thechamber 1. However, the positions of the gas feeder 5, the controller 6,the gas supplying port 1 a and the gas discharging port 1 b areschematically shown in FIG. 1B.

FIG. 1B illustrates plural wafers (nine wafers in this case) W₁ to W₉disposed on the same stage 3. Reference symbols P₁ to P₉ respectivelydenote the positions the wafers W₁ to W₉ on the stage 3.

FIGS. 1A and 1B illustrate an X direction and a Y direction which areparallel to the top surface of the stage 3 and are perpendicular to eachother, and a Z direction which is perpendicular to the top surface ofthe stage 3. In this specification, +Z direction is treated as an upperdirection, and −Z direction is treated as a lower direction. Forexample, a positional relationship between the stage 3 and the wafers W₁to W₉ is expressed such that the stage 3 is located below the wafers W₁to W₉. In the present embodiment, −Z direction may match the gravitydirection, or may not match the gravity direction.

The wafers W₁ to W₉ are set on the stage 3 according to the followingprocedure. First, a wafer cassette containing the wafers W₁ to W₉ isloaded to the cassette loading module 2. Next, the conveying arm 4retrieves the wafers W₁ to W₉ from the wafer cassette, conveys thewafers W₁ to W₉ into the chamber 1, and sets the wafers W₁ to W₉ on thestage 3. The retrieval, the conveyance and the setting of the wafers W₁to W₉ are conducted for respective wafers W₁ to W₉ in order. The wafersW₁ to W₉ are respectively set at the positions P₁ to P₉ on the stage 3.

Thereafter, the wafers W₁ to W₉ on the stage 3 are treated in thechamber 1 simultaneously. Examples of the treatment include depositionsuch as chemical vapor deposition (CVD) and physical vapor deposition(PVD), etching such as reactive ion etching (RIE), oxidization,nitridization, coating, epitaxial growth, impurity implantation,annealing, ashing and the like. At this time, the gas feeder 5 suppliesa gas for these treatments into the chamber 1 via the gas supplying port1 a. The gas in the chamber 1 is discharged from the gas dischargingport 1 b.

After the treatment of the wafers W₁ to W₉ is finished, the conveyingarm 4 conveys the wafers W₁ to W₉ out of the chamber 1, and storing thewafers W₁ to W₉ into the wafer cassette. The conveyance and the storingof the wafers W₁ to W₉ are conducted for respective wafers W₁ to W₉ inorder.

The controller 6 controls various operations of the semiconductormanufacturing apparatus. More specifically, the controller 6 controlsthe conveyance of the wafer W₁ to W₉ into and out of the chamber 1 withthe conveying arm 4 and the supply of the gas with the gas feeder 5.When there are devices such as a cooling device, a heating device, andan electrode for the wafers W₁ to W₉ in the semiconductor manufacturingapparatus, the controller 6 also controls the operations of thesedevices. The details of the operation of the controller 6 will beexplained later.

An example of the stage 3 of the present embodiment is a large stage onwhich large wafers are set. An example of the wafers W₁ to W₉ of thepresent embodiment is small wafers. Therefore, according to the presentembodiment, plural wafers W₁ to W₉ can be set on the same stage 3.

FIGS. 2A to 2C are drawings for explaining a semiconductor manufacturingmethod of the first embodiment.

FIG. 2A illustrates a semiconductor manufacturing method of a firstcomparative example of the first embodiment. The semiconductormanufacturing method of FIG. 2A is executed by a single-wafer treatmentapparatus. In FIG. 2A, the wafers W₁ to W₄ are individually treated foreach wafer. Therefore, total treatment time T of the wafers W₁ to W₄ ofthe first comparative example is given by the following expression (1).

T=(T ₁ +T ₂ +T ₃)N   (1)

Reference symbol T₁ indicates conveyance time required to convey eachwafer into and out of the chamber 1. The reference symbol T₂ indicatestreatment preparation time required for treatment preparation of eachwafer. An example of the treatment preparation includes vacuumevacuation in the chamber 1. Reference symbol T₃ indicates treatmenttime required to actually treat each wafer. Reference symbol N indicatesthe number of wafers W₁ to W₄ (N=4 in this case).

FIG. 2B is a semiconductor manufacturing method of a second comparativeexample of the first embodiment. The semiconductor manufacturing methodof FIG. 2B is executed by a batch treatment apparatus. In FIG. 2B, thewafers W₁ to W₄ are treated simultaneously. Therefore, the totaltreatment time T of the wafers W₁ to W₄ of the second comparativeexample is given by the following expression (2).

T=T ₁ N+T ₂ +T ₃   (2)

In the first comparative example, the conveyance, the treatmentpreparation and the treatment of the wafers W₁ to W₄ are executedrepeatedly N times. On the other hand, according to the secondcomparative example, the conveyance of the wafers W₁ to W₄ are executedrepeatedly N times while the treatment preparation and the treatment ofthe wafers W₁ to W₄ are executed collectively and simultaneously.Therefore, according to the second comparative example, the totaltreatment time T of the wafers W₁ to W₄ can be reduced. However, thetreatment speeds of the wafers W₁ to W₄ differ according to thepositions of the wafers W₁ to W₄ in the batch treatment apparatus, andtherefore the characteristics of the wafers W₁ to W₄ may vary in thesecond comparative example.

FIG. 2C illustrates the semiconductor manufacturing method of the firstembodiment. The semiconductor manufacturing method of FIG. 2C isexecuted by the semiconductor manufacturing apparatus of FIGS. 1A and1B.

In the present embodiment, the wafers W₁ to W₄ are set on the same stage3 and are treated simultaneously. However, the controller 6 of thepresent embodiment divides the treatment time T₃ of this treatment intothe first to N-th treatment periods, and the positions of the wafers W₁to W₄ on the stage 3 are changed by the conveying arm 4 according to thetreatment periods. Each treatment period of the present embodiment isT₃/N. An arrow A indicates how the positions of the wafers W₁ to W₄ arechanged. The total treatment time T of the wafers W₁ to W₄ of thepresent embodiment is given by the following expression (3).

$\begin{matrix}\begin{matrix}{T = {\left( {{T_{1}N} + T_{2} + {T_{3}/N}} \right)N}} \\{= {{T_{1}N^{2}} + {T_{2}N} + T_{3}}}\end{matrix} & (3)\end{matrix}$

In the present embodiment, the positions of the wafers W₁ to W₄ arechanged for each treatment period, and therefore the conveyance time ofthe wafers W₁ to W₄ before each treatment period is T₁N. In the presentembodiment, the treatment preparation of the wafers W₁ to W₄ for eachtreatment period is performed once, and therefore the treatmentpreparation time of the wafers W₁ to W₄ before each treatment period isT₂. The treatment time of the wafers W₁ to W₄ of each treatment periodis T₃/N as described above. Therefore, the total treatment time T of thewafers W₁ to W₄ of the present embodiment is obtained by multiplying thesummation of the conveyance time, the treatment preparation time and thetreatment time by N, and is given as shown in the above expression (3).

As can be understood from the expression (2) and the expression (3), thetotal treatment time T of the present embodiment is longer than thetotal treatment time T of the second comparative example (batchtreatment). However, as can be understood from the expression (1) andthe expression (3), the total treatment time T of the present embodimentmay become shorter than the total treatment time T of the firstcomparative example (single-wafer treatment) depending on the values ofthe conveyance time T₁ of each wafer, treatment time T₃ of each wafer,and the wafer number N. In the present embodiment, variation in thecharacteristics of the wafers W₁ to W₄ can be suppressed by changing thepositions of the wafers W₁ to W₄ during the treatment of the wafers W₁to W₄. Therefore, according to the present embodiment, the plural wafersW₁ to W₄ can be treated in a short time while the variation in thecharacteristics of the wafers W₁ to W₄ can be suppressed.

The arrow A of FIG. 2C indicates how the positions of the wafers W₁ toW₄ are changed. In the present embodiment, the positions of the wafersW₁ to W₄ are changed so that the positions of the wafers W₁ to W₄ areswitched with one another.

For example, in the first treatment period, the wafers W₁, W₂, W₃ and W₄are set at positions P₁, P₂, P₃ and P₄, respectively. In the secondtreatment period, the positions of the wafer W₁, W₂, W₃ and W₄ arechanged to positions P₂, P₃, P₄ and P₁, respectively. In the thirdtreatment period, the positions of the wafers W₁, W₂, W₃ and W₄ arechanged to positions P₃, P₄, P₁ and P₂, respectively. In the fourthtreatment period, the positions of the wafers W₁, W₂, W₃ and W₄ arechanged to positions P₄, P₁, P₂ and P₃, respectively. Therefore,according to the present embodiment, the variation in thecharacteristics of the wafers W₁ to W₄ can be suppressed.

However, when the positions of the wafers W₁ to W₄ are switched with oneanother, some of the wafers W₁ to W₄ may be set at the same positionsagain. For example, the positions of the wafers W₁, W₂, W₃ and W₄ may bechanged from the positions P₁, P₂, P₃ and P₄ to the positions P₂, P₃, P₁and P₄, respectively. For example, when the wafer at the position P₄ istreated so as to obtain average characteristics, the position of thewafer at the position P₄ may not be changed. Therefore, when changingthe positions of the wafers W₁ to W₄, the positions of all the wafers W₁to W₄ may be changed, or only the position(s) of a part of the wafers W₁to W₄ may be changed.

The controller 6 of the present embodiment may divide the treatment timeT₃ into the first to K-th treatment periods which are less than thewafer number N (K<N). In this case, each treatment period is T₃/K, andthe change of the positions of the wafers W₁ to W₄ is executed K times.For example, when the wafer at the position P₄ is treated so as toobtain average characteristics, the change of the positions of thewafers at the positions P₁ to P₃ may be executed only three times.

The division performed K times which are less than the wafer number N asdescribed above may also be applied to a case where it is not necessaryto completely eliminate the variation in the characteristics of thewafers W₁ to W₄ and it is sufficient to somewhat reduce the variation inthe characteristics of the wafers W₁ to W₄.

The treatment time T₃ of the present embodiment may be divided equallyinto the first to K-th treatment periods or may be divided unequallyinto the first to K-th treatment periods. For example, when thetreatment time T₃ is divided into the first to third treatment periods,the first, second and third treatment periods may be set to T₃/4, T₃/2and T₃/4, respectively.

In the present embodiment, the positions of the wafers W₁ to W₄ may bechanged using a method other than switching of the positions of thewafers W₁ to W₄. For example, the positions of the wafers W₁, W₂, W₃ andW₄ may be respectively changed from the position P₁, P₂, P₃ and P₄ tothe positions P₂, P₃, P₄ and P_(X). The position P_(X) is a positiondifferent from the positions P₁ to P₄. An example of such method will beexplained in a second embodiment described later.

The variation in the characteristics of the wafers W₁ to W₄ isconsidered to be caused due to the position of the gas supplying port 1a, the position of the gas discharging port 1 b, the positions ofelectrodes in the chamber 1 and the like. Therefore, when designing theorder of changing the positions of the wafers W₁ to W₄ or designing thedivision number K of the treatment period, it is desired to make adesign by taking such factors into consideration.

FIG. 3 is a graph for explaining advantages of the semiconductormanufacturing method of the first embodiment.

The horizontal axis of FIG. 3 indicates the wafer number N. The verticalaxis of FIG. 3 indicates the total treatment time T. Reference symbolsC₁, C₂ and C₃ indicates the total treatment time T in a case of thefirst comparative example of FIG. 2A, a case of the second comparativeexample of FIG. 2B, and a case of the present embodiment of FIG. 2C,respectively. However, the division number of the treatment period inthese cases is the same as the wafer number N.

In FIG. 3, the conveyance time T₁ is set to 1, the treatment preparationtime T₂ is set to 3, and the treatment time T₃ is set to 10. In thiscase, when the wafer number N is less than 10, the total treatment timeT of the present embodiment is less than the total treatment time T ofthe first comparative example. Therefore, it is understood that thesemiconductor manufacturing method of the present embodiment is suitablefor cases where a small number of wafers are treated simultaneously,e.g., a case where small wafers are treated.

A condition in which the total treatment time T of the presentembodiment is less than the total treatment time T of the firstcomparative example can be derived according to the following expression(4).

T ₁ N ² +T ₂ N+T ₃<(T ₁ +T ₂ +T ₃)N   (4)

If the expression (4) is solved, the condition of the wafer number N isgiven according to the following expression (5).

N<T ₃ /T ₁   (5)

FIGS. 4A and 4B are cross sectional view for explaining advantages ofthe semiconductor manufacturing method of the first embodiment.

FIG. 4A illustrates wafers W₁ and W₂ treated according to the secondcomparative example. An example of this treatment is deposition such asCVD and PVD. Each of the wafers W₁ and W₂ includes a substrate 11 and adeposition film 12 formed on the substrate 11. However, the thicknessesof the deposition films 12 of the wafers W₁ and W₂ are D₁ and D₂(D₁<D₂), respectively. In this manner, the thicknesses of the depositionfilms 12 vary between the wafers W₁ and W₂ in the second comparativeexample.

FIG. 4A illustrates wafers W₁ and W₂ treated according to the presentembodiment. In the present embodiment, the treatment time T₃ of eachwafer is divided into the first and second treatment periods, and thepositions of the wafers W₁ and W₂ are switched between the treatmentperiods. Therefore, each of the wafers W₁ and W₂ includes a substrate11, a first deposition film 12 a formed in the first treatment period,and a second deposition film 12 b formed in the second treatment period.Any of the thicknesses of the deposition films 12 of the wafers W₁ andW₂ is D₁/2+D₂/2. In this manner, the present embodiment makes itpossible to suppress the variation of the thicknesses of the depositionfilms 12 of the wafers W₁ and W₂.

As described above, the controller 6 of the present embodiment dividesthe treatment time for simultaneously treating the plural wafers on thestage 4 into plural treatment periods, and changes the positions of theplural wafers on the stage 4 by the conveying arm 4 for each treatmentperiod. Therefore, according to the present embodiment, the pluralwafers can be treated in a short time while the variation of thecharacteristics of the wafers can be suppressed. According to thepresent embodiment, such treatment can be achieved without changing theusage of the semiconductor manufacturing apparatus and the contents ofthe treatment.

Some of the steps of the semiconductor manufacturing method of thepresent embodiment may be executed manually by a worker instead of beingexecuted automatically by the semiconductor manufacturing apparatus. Forexample, the conveyance of the wafers into and out of the chamber 1 andthe change of the positions of the wafers may be executed by a workerinstead of the conveying arm 4.

Second Embodiment

FIG. 5 is a drawing for explaining a semiconductor manufacturing methodof a second embodiment. The semiconductor manufacturing method of thepresent embodiment is executed by the semiconductor manufacturingapparatus of FIGS. 1A and 1B.

In the first embodiment, the treatment time of the wafers is dividedinto plural treatment periods in order to suppress the variation in thecharacteristics of the wafers. On the other hand, in the presentembodiment, the treatment time of the wafers is divided into pluraltreatment periods in order to give desired characteristics to eachwafer. In other words, in the present embodiment, the variation of thecharacteristics of the wafers is not suppressed, but the variation ofthe characteristics of the wafers is utilized.

The controller 6 of the present embodiment can access to a lotinformation database (DB) 21, a process amount DB 22 as an example of aprocess amount storage module, and a process characteristics DB 23. Forexample, the lot information DB 21, the process amount DB 22 and theprocess characteristics DB 23 are stored in a server which is connectedwith the semiconductor manufacturing apparatus via a network.

The lot information DB 21 stores, for example, the number N of thewafers W₁ to W₄ simultaneously treated by the semiconductormanufacturing apparatus. The process amount DB 22 stores process amountD₁ to D₄ of the wafers W₁ to W₄ in this treatment. Examples of theprocess amounts include a thickness of a deposition film in adeposition, an etching amount of a process target film in an etching,and a dose amount of impurity in an impurity implantation.

The process characteristics DB 23 stores process characteristics of thesemiconductor manufacturing apparatus when the semiconductormanufacturing apparatus treats the wafers W₁ to W₄. FIG. 5 illustrates,as an example of such process characteristics, relationship between aposition of a wafer and a thickness of a deposition film. FIG. 5indicates that when the wafer is set in a central position of the stage3, the thickness of the deposition film becomes thicker, and when thewafer is set in a peripheral portion of the stage 3, the thickness ofthe deposition film becomes thinner. FIG. 5 further illustrates, as anexample of the process characteristics, relationship between the time ofthe deposition and the thickness of the deposition film.

When the treatment time of the wafers is divided into the first to K-thtreatment periods where K is an integer of two or more, the controller 6accesses the lot information DB 21, the process amount DB 22 and theprocess characteristics DB 23. The controller 6 then determines thedivision number K of the treatment periods, the length of each treatmentperiod, the positions of the wafers W₁ to W₄ in each treatment periodand the like, based on the information in the databases 21 to 23. Thecontroller 6 manages the determined contents as a process sequence, andcontrols the treatment of the wafers W₁ to W₄ in accordance with theprocess sequence.

FIG. 5 shows, as the information included in the process sequence, thewafer positions, the treatment preparation time and the treatment timein the first treatment period, and the wafer positions, the treatmentpreparation time and the treatment time in the second treatment period.The wafer position of each wafer indicates an X coordinate and a Ycoordinate on the stage 3. In FIG. 5, as it is understood by comparingthe coordinates in the first treatment period and the coordinates in thesecond treatment period, the positions of the wafers W₁ to W₄ arechanged by using a method other than switching.

The controller 6 of the present embodiment generates the processsequence so that the process amounts of the wafers W₁ to W₄ in the firstto K-th treatment periods respectively become the process amounts D₁ toD₄, and controls the treatment of the wafers W₁ to W₄ in accordance withthe process sequence. For example, when the process amounts D₁ to D₄indicate the thicknesses of the deposition films, the thicknesses of thedeposition films of the wafers W₁ to W₄ respectively become thethicknesses D₁ to D₄ after the treatment in the first to K-th treatmentperiods is finished. In this manner, according to the presentembodiment, desired characteristics can be given to the wafers W₁ to W₄by using the variation in the characteristics of the wafers W₁ to W₄.

When the controller 6 of the present embodiment generates the processsequence, the controller 6 of the present embodiment also accesses thelot information DB 21 and the process characteristics DB 23. The wafernumber N in the lot information DB 21 is used to determine, for example,the division number K of the treatment periods. The information in theprocess characteristics DB23 is used to determine, for example, thepositions of the wafers W₁ to W₄. For example, when the deposition filmof any given wafer is desired to be thicker, the wafer is set in thecentral portion of the stage 3 for a longer period of time. Since theprocess characteristics of the semiconductor manufacturing apparatusalso depends on the wafer number N, the wafer number N in the lotinformation DB 21 can also be used to determine the positions of thewafers W₁ to W₄ and the like.

FIG. 6 is a block diagram for explaining operation of the controller 6of the second embodiment.

The controller 6 of the present embodiment includes a lot operationmodule 31, a work-start command module 32, a process amountdetermination module 33, a process sequence generator 34 and a processcontroller 35.

The lot operation module 31 receives a work-start operation for startingthe treatment of the wafers W₁ to W₄ from a worker who operates thesemiconductor manufacturing apparatus. In this case, the work-startcommand module 32 determines a treatment method of the wafers W₁ to W₄,and transmits a work-start command of the determined treatment method.For example, the work-start command module 32 determines whether thedividing procedure explained above is to be applied to the treatment ofthe wafers W₁ to W₄.

The process amount determination module 33 accesses the lot informationDB 21 to determine whether the number N of the wafers W₁ to W₄ is two ormore. The process amount determination module 33 further accesses theprocess amount DB 22 to determine whether the process amount D₁ to D₄ ofthe wafers W₁ to W₄ are the same or not. The determination results ofthe process amount determination module 33 are sent to the work-startcommand module 32 and the process sequence generator 34.

The process sequence generator 34 accesses the lot information DB 21,the process amount DB 22, the process characteristics DB 23 and aprocess recipe DB 24 to generate the process sequence for achieving theprocess amount D₁ to D₄ of the wafers W₁ to W₄. The information in theprocess characteristics DB 23 is preliminarily set by an apparatusadministrator of the semiconductor manufacturing apparatus.

The process recipe DB 24 is, for example, stored in the server connectedto the semiconductor manufacturing apparatus via the network. Theprocess recipe DB 24 stores process recipes for treating the wafers W₁to W₄. Examples of the process recipes include a type of a gas, a flowrate of a gas, and a heating temperature of the wafers W₁ to W₄.

The process controller 35 controls the treatment of the wafers W₁ to W₄.For example, when the process amounts D₁ to D₄ of the wafers W₁ to W₄are the same, the treatment of the wafers W₁ to W₄ is controlled asexplained in the first embodiment. When the process amounts D₁ to D₄ ofthe wafers W₁ to W₄ are different, the treatment of the wafers W₁ to W₄is controlled in accordance with the process sequence as explained inthe second embodiment.

FIG. 7 is a flowchart for explaining the semiconductor manufacturingmethod of the second embodiment.

When the lot operation module 31 receives the work-start operation (stepS1), the process amount determination module 33 refers to the lotinformation DB 21 (step S2), and determines whether the number N ofwafers W₁ to W₄ is two or more (step S3).

When the wafer number N is determined to be one, the work-start commandmodule 32 transmits the work-start command for treating the wafer withnon-dividing procedure (step S11), and the process controller 35 treatsthe wafer in accordance with the work-start command (step S12).

When the number N of wafers W₁ to W₄ is determined to be two or more,the process amount determination module 33 refers to the process amountDB 22 (step S4), and determines whether the process amounts D₁ to D₄ ofthe wafers W₁ to W₄ are the same or not (step S5).

When the process amounts D₁ to D₄ of the wafers W₁ to W₄ are determinedto be the same, the work-start command module 32 transmits thework-start command for processing the wafers W₁ to W₄ with the dividingprocedure of the first embodiment (step S11), and the process controller35 treats the wafers W₁ to W₄ in accordance with the work-start command(step S12).

When the process amounts D₁ to D₄ of the wafers W₁ to W₄ are different,the process sequence generator 34 refers to the process recipe DB 24(step S6), and determines whether the process recipes of the wafers W₁to W₄ are the same or not (step S7).

When the process recipes of the wafers W₁ to W₄ are determined to bedifferent, the wafers W₁ to W₄ cannot be treated simultaneously, andtherefore the process sequence generator 34 divides the wafers W₁ to W₄into groups of wafers processed by the same recipes (step S21). Then,the procedure in step S2 and subsequent steps is executed again on thedivided groups of wafers.

When the process recipes of the wafers W₁ to W₄ are determined to be thesame, the process sequence generator 34 refers to the processcharacteristics DB 23 and the like (step S8), and generates the processsequence for achieving the process amounts D₁ to D₄ of the wafers W₁ toW₄ (step S9). Subsequently, the work-start command module 32 transmitsthe work-start command for treating the wafers W₁ to W₄ with thedividing procedure of the second embodiment (step S11), and the processcontroller 35 treats the wafers W₁ to W₄ in accordance with the processsequence (step S12).

As described above, the controller 6 of the present embodiment changesthe positions of the wafers W₁ to W₄ in each treatment period so thatthe process amounts of the wafers W₁ to W₄ by the treatment in the firstto K-th treatment periods respectively become the process amounts D₁ toD₄. Therefore, according to the present embodiment, the wafers W₁ to W₄can be treated in a short time while desired characteristics can begiven to the wafers W₁ to W₄.

In the second embodiment, the division number K of the treatment periodsmay be more than the wafer number N (K>N). This makes it possible, forexample, to give desired characteristics to the wafers W₁ to W₄ with ahigher degree of precision. This is also applicable to the firstembodiment.

As described above, according to the first and second embodiments,plural wafers can be appropriately treated in a short time.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel apparatuses and methodsdescribed herein may be embodied in a variety of other forms;furthermore, various omissions, substitutions and changes in the form ofthe apparatuses and methods described herein may be made withoutdeparting from the spirit of the inventions. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the inventions.

1. A semiconductor manufacturing apparatus comprising: a stage providedin a chamber; a conveying module configured to convey a plurality ofwafers into the chamber and to set the plurality of wafers on the stage;a controller configured to divide treatment time for simultaneouslytreating the plurality of wafers on the stage into first to K-thtreatment periods where K is an integer of two or more, and to changepositions of one or more of the plurality of wafers on the stage by theconveying module according to the treatment periods.
 2. The apparatus ofclaim 1, wherein the division number K of the first to K-th treatmentperiods is equal to a number of the plurality of wafers.
 3. Theapparatus of claim 1, wherein the division number K of the first to K-thtreatment periods is less than a number of the plurality of wafers. 4.The apparatus of claim 1, wherein the controller changes the positionsof the wafers so that the positions of the wafers are switched with eachother.
 5. The apparatus of claim 1, wherein the plurality of wafersinclude first to N-th wafers where N is an integer of two or more, andthe controller accesses a process amount storage module configured tostore first to N-th process amounts for the first to N-th wafers, andchanges the positions of one or more of the first to N-th wafers so thatprocess amounts of the first to N-th wafers in the first to K-thtreatment periods respectively become the first to N-th process amounts.6. The apparatus of claim 5, wherein the controller accesses a waferinformation storage module configured to store a number of the pluralityof wafers, and determines the division number K of the first to K-thtreatment periods based on the number of the plurality of wafers.
 7. Theapparatus of claim 5, wherein the controller accesses a processcharacteristics storage module configured to store a processcharacteristic of the semiconductor manufacturing apparatus forprocessing the wafers, and determines the positions of the wafers basedon the process characteristic.
 8. The apparatus of claim 5, wherein theprocess amounts are amounts related to formation of a film onto thewafers, removal of a film on the wafers, or impurity implantation to thewafers.
 9. The apparatus of claim 1, wherein the controller equallydivides the treatment time into the first to K-th treatment periods. 10.The apparatus of claim 1, wherein the controller unequally divides thetreatment time into the first to K-th treatment periods.
 11. Asemiconductor manufacturing method comprising: conveying a plurality ofwafers into a chamber; setting the plurality of wafers on a stage in thechamber; and dividing treatment time for simultaneously treating theplurality of wafers on the stage into first to K-th treatment periodswhere K is an integer of two or more, and changing positions of one ormore of the plurality of wafers on the stage according to the treatmentperiods.
 12. The method of claim 11, wherein the division number K ofthe first to K-th treatment periods is equal to a number of theplurality of wafers.
 13. The method of claim 11, wherein the divisionnumber K of the first to K-th treatment periods is less than a number ofthe plurality of wafers.
 14. The method of claim 11, wherein thepositions of the wafers are changed so that the positions of the wafersare switched with each other.
 15. The method of claim 11, wherein theplurality of wafers include first to N-th wafers where N is an integerof two or more, and the method further comprises accessing a processamount storage module configured to store first to N-th process amountsfor the first to N-th wafers, and changing the positions of one or moreof the first to N-th wafers so that process amounts of the first to N-thwafers in the first to K-th treatment periods respectively become thefirst to N-th process amounts.
 16. The method of claim 15, furthercomprising accessing a wafer information storage module configured tostore a number of the plurality of wafers, and determining the divisionnumber K of the first to K-th treatment periods based on the number ofthe plurality of wafers.
 17. The method of claim 15, further accessing aprocess characteristics storage module configured to store a processcharacteristic of a semiconductor manufacturing apparatus for processingthe wafers, and determining the positions of the wafers based on theprocess characteristic.
 18. The method of claim 15, wherein the processamounts are amounts related to formation of a film onto the wafers,removal of a film on the wafers, or impurity implantation to the wafers.19. The method of claim 11, wherein the treatment time is equallydivided into the first to K-th treatment periods.
 20. The method ofclaim 11, wherein the treatment time is unequally divided into the firstto K-th treatment periods.